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VV5430
(R)
Monochrome Analog Output CMOS Image Sensors
DESCRIPTION
The VV5430 is a highly-integrated VLSI camera device based on the unique CMOS sensor technology from STMicroelectronics. It delivers a fully-formatted composite monochrome video signal. Standards options include EIA (320 x 244) and CCIR (384 x 287). It is possible to develop a single chip video camera using this device that requires only supply voltage in, and delivers composite video out for connection to a video monitor. The integrated 75 driver eliminates the need for additional active components to drive standard loads, including double terminated lines. It is also suitable for applications requiring the digitisation of the video signal or external microprocessor control. In the VV5430 Frame, Line and Pixel timing signals are provided to facilitate pixel-locked digitisation of the analog video data. In addition to the these outputs a synchronisation input (SIN) is also provided to allow the start of frame to be synchronised to an external event. The device features automatic exposure control that allows a fixed-aperture lens to be used, and incorporates Normal and Backlit modes to give operation over a wide range of scene types. A bi-directional serial interface on the VV5430 allows an external controller to set operational parameters and control exposure and gain values directly.
KEY FEATURES
* * * * * * * * * * * Complete Video Camera on a single chip Minimal support circuit EIA/CCIR standard compatible options Low power operation - single voltage supply Integral 75 ohm driver 384 x 287 pixel array Automatic exposure and gain control Linear or gamma corrected output option Automatic black level calibration Serial Interface Control Frame and line timing signals for external ADC
APPLICATIONS
* * * * Security/Observation systems Biometric identification Toys and games Digital Image capture systems
SPECIFICATIONS
Pixel resolution 384 x 287 (CCIR) 320 x 243 (EIA)
Array size
4.66mm x 3.54mm
0.5 lux
DEVICE FUNCTIONALITY
Min. illumination
(min. detectable signal)
AGC AEC RESE TB LIN BKLIT CCIR
Exposure control Gain control Signal/Noise ratio Supply voltage Supply current Operating temperature (ambient) Package type
Automatic (to 146000:1) Automatic (to +20dB) 46dB 5.0v DC +/- 5% <45mA 0oC - 40oC
(for extended temp. info please contact STMicroelectronics)
V E R T IC A L S H IF T R E G IS TE R
P H O TO D IO D E A R R A Y
D IG ITA L C O N TR O L LO G IC .
CKOUT CKIN SIN CPE FST LST PV PVB ODD SDA SCL SAB0 SAB1 C LO C K C IR C U IT C O LU M N S E N S E A M P LIF IE R S
A N A LO G V O LT A G E R E FS .
VRT Vbloom VOFF VBG EBCK EVW T 2V7 AVO
IM A G E C A P TU R E
V ID E O B U F FE R S A M P LE & H O LD
48LCC
5V S E R IA L I/F H O R IZO N TA L S H IFT R E G IS T E R V ID E O AM P
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VV5430
Table of Contents
1. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 2. Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2.1 Device Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 Defect Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3. Device Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3.1 Package Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3.2 Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.3 Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4. Video Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 4.1 Video Signal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5. Control Signals for Image Digitisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1 Image Capture Control Signal Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6. Shuffle Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 6.1 Quarter mode output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.2 Quarter mode line timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 7. Exposure Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.1 Automatic Exposure Control (AEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.2 Automatic Gain Control (AGC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.3 Backlit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8. Serial Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 8.1 Serial Communication Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 9. Read data from camera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 10. Write to Camera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 10.1 Timing Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 10.2 Header Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 10.3 Message content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 11. Example Support Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 12. Ordering Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
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VV5430
Revision History
1.
Revision History
The following is a list of specific changes made to this datasheet since the previous revisions. It does not include general fomatting changes, but is intended to highlight changes that may affect device operation in a customer system.
Section
2
Change
Removed obsolete test descriptions Corrected Defect Specification Added reference to generating SIN on only odd or only evenfields, not both. Setup Code 1: Bit 10 was incorrectly described. This bit should be set to 0 for normal operation.
6 10
Table 1 : Revision History
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CD5430F-A
Specifications
VV5430
2.
Specifications
2.1
Device Specifications
1.0 0.8 0.6 0.4 0.2 1000 400 500 600 700 800 900 1100 0
Normalised Response
Illumination Colour Temp. Clock Frequency Exposure Gain Auto. Gain Control (AGC) Correction mode
3200o K Std. CCIR Maximum x1 Off Linear
Wavelength nm
Figure 1 : Spectral Response
The sensor is tested using the example support circuit illustrated later in this document. Standard imaging conditions used for optical tests employ a tungsten halogen lamp to uniformly illuminate the sensor (to better than 0.5%), or to illuminate specific areas. A neutral density filter is used to control the level of illumination where required.
Parameter
Supply Voltage Voltage on other input pins Ambient Operating Temperature
(contact STMicroelectronics for extended temp. ranges)
Value
-0.5 to +7.0 volts -0.5 to VDD + 0.5 volts 0oC to 40oC -30oC to 125oC 10mA (per o/p, one at a time, 1sec. duration)
Storage Temperature Maximum DC TTL output Current Magnitude
Table 2 : Absolute Maximum Ratings Note: Stresses exceeding the Absolute Maximum Ratings may induce failure. Exposure to absolute maximum ratings for extended periods may reduce reliability. Functionality at or above these conditions is not implied.
Symbol
VDD VIH VIL TA
Parameter
Operating supply voltage Input Voltage Logic "1" Input Voltage Logic "0" Ambient Operating Temperature
Min.
4.75 2.4 -0.5 0
Typ.
5.0
Max.
5.25 VDD+0.5 0.8 40
Units
Volts Volts Volts
o
Notes
C
Still air
Table 3 : DC Operating Conditions
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VV5430
Specifications
Symbol
CKIN CKIN SCL
Parameter
EIA Crystal frequency CCIR Crystal frequency Serial Data Clock
Min .
Typ.
12.0000 14.7456
Max.
Unit s
MHz MHz
Note s
1 1 2
100
KHz
Table 4 : AC Operating Conditions 1. Pixel Clock = CKIN/2 2. Serial Interface clock must be generated by host processor.
Symbol
IDCC IADD IDD VREF2V7 VBG VOH VOL IILK
Parameter
Digital supply current Analog supply current Overall supply current Internal voltage reference Internal bandgap reference Output Voltage Logic "1" Output Voltage Logic "0" Input Leakage current
Min.
Typ.
10 25 35 2.700 1.22
Max.
Unit s
mA mA mA Volts Volts Volts
Notes
1 1 1
2.4 0.6 -1 1
IOH = 2mA IOL = -2mA VIH on input VIL on input
Volts A A
Table 5 : Electrical Characteristics Typical conditions, VDD = 5.0 V, TA = 27oC 1. Digital and Analogue outputs unloaded - add output current.
Parameter
Dark Current Signal
min.
typ.
50
max.
units
mV/Sec
Note
Modal pixel voltage due to photodiode leakage under zero illumination with Gain=1 (Vdark = (Vt1 - Vt2)/(t1-t2), calculated over two different frames VAve/Lux*10ms, where Lux gives 50% saturation with Gain=1 and Exposure=10ms Minimum detectable illumination with Standard CCIR clock
Sensitivity Min. Illumination
6 0.5
V/Lux*Sec Lux
Note: Devices are normaly not 100% tested for the above characterisation parameters, other than Dark Current Signal. Table 6 : Operating characteristics
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Specifications
VV5430
2.2
Defect Specification
A Defect is an area of pixels that produces output significantly different from its surrounding pixels for the same illumination level. The definition of a Defect Pixel varies according to testing conditions as follows:
Test
Black Image Test Light Image Test
Exposure
Minimum Mid range
Illumination
Black 66% Sat.
Defective Pixel output definition
Differing more than 8%. from modal value. Differing more than 4% from modal value.
The pixel area of the sensor is divided into the following areas to qualify the defect specification:
Area A
Area B
Where Area A is the inner 50% of the image area The defect specification is then defined as follows:
Image Area
Area A Area B
Max. No. of Defectes
0 4 1
Notes
This is the most critical image area Unconnected single pixels Of up to four connected pixels (2x2 max.)
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VV5430
Device Details
3. 3.1
Device Details Package Details 0.51 TYP 1.56 TYP 0.5min, 0.6max 0.90min, 1.12max 13.7
Glass Lid Die Base
Viewed from side 14.22
The optical array is centred within the package to a tolerance of 0.2 mm, and rotated no more than 0.5o Unless otherwise stated, tolerances on package dimensions 10%
2.16 PIN 1 1.016 PITCH TYP
Glass lid placement is controlled so that no package overhang exists. All dimensions in millimetres Refractive index of glass approx 1.52
Viewed from below
3.2 Pinout Diagram
RESETB
CKOUT
BKLIT
SAB0
CCIR
CKIN
AGC
VDD
LST
AEC
VSS
30 29 28 27 26 25 24 23 22 21 20 19 VSS 31 PV 32 PVB 33 VDD 34 CPE 35 FST 36 Viewed from top of package ODD 37 SCI 38 SCL 39 SDA 40 VDD 41 VSS 42 43 44 45 46 47 48 1 VBLWT VBLOOM VRT VCM VREF2V7 AGND 2 3 VOFF/ VPED 4 DEC2V2 5 DEC2V7 6 DNC
LIN 18 SCE 17 SIN 16 SAB1 15 VGND 14 AVO 13 VVDD 12 AMP2 11 AMP1 10 AVSS 9 8 7 EVWT EBCK AVDD
48 Pin LCC
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AVCC VBG
Device Details
VV5430
3.3
Pin List
Pin
Signal Name
Typ e
POWER SUPPLIES
Description
1 7 10 13 15 24,31 27,34 41 42 48
AVCC AVDD AVSS VVDD VGND VSS VDD DVDD DVSS AGND
PWR PWR GND PWR GND GND PWR PWR GND GND
Core analogue power and reference supplies. Output stage power. AVDD3 output stage logic. Output stage ground. AVSS3 output stage logic. 75ohm buffer supply. 75ohm buffer ground. Digital padring & logic ground. Digital padring & logic power. Core digital power. Core digital ground. Core analogue ground and reference supplies. ANALOGUE VOLTAGE REFERENCES
2 3 4 5 6 8 9 43 44 45 46 47
VBG VOFF/VPED DEC2V2 DEC2V7 EBCK EVWT VBLWT VBLOOM VRT VCM VREF2V7
OA IA OA OA DNC IA IA IA OA IA IA OA
Internal bandgap reference voltage (1.22V nominal). Requires external 0.1uF capacitor. Pedestal DAC & offset comp. DAC bias. Connect to VBG or external reference. Decouple 2.2V reference. Requires external 0.1uF capacitor. Decouple 2.7V reference. Requires external 0.1uF capacitor. Do NOT connect - for test use only External black level bias. Internally generated. Decouple to VGND External white pixel threshold for exposure control. Decouple to VGND Defines white level for clamp circuitry. Requires external 0.1uF capacitor. Anti-blooming voltage reference. Requires external 0.1uF capacitor. Pixel reset voltage. Connect to VREF2V7 or external reference. Offset DAC common mode input. Connect to VREF2V7. Internally generated 2.7V reference. Requires external 4.7uF capacitor. ANALOGUE OUTPUTS
14
AVO
OA
Buffered Analogue video out. Can drive a doubly terminated 75ohm load. SYSTEM CLOCKS
25 26
CKOUT CKIN
OD ID
Oscillator output. Connect Crystal for standard timing. Oscillator input. Connect Crystal for standard timing. IMAGE CAPTURE TIMING SIGNALS
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VV5430
Device Details
Pin
30 32 33 35 36 37
Signal Name
LST PV PVB CPE FST ODD
Typ e
OD OD OD ID OD OD
Description
Line start. Active high pulse (start of active video lines). Pixel sample clock. Qualifies video output for external image capture. Pixel sample clock bar. Inverse of PV. Pixel sample clock enable. Default CPE = 0 i.e. PV/PVB disabled. Field start. Synchronises external image capture. Odd/even field signal. (ODD = 1 for odd fields, ODD = 0 for even) DIGITAL CONTROL SIGNALS
16 17 18 19
SAB1 SIN SCE LIN
ID ID ID ID
Higher bit of two least significant bits of device address on serial interface. Used to reset video timing control logic without resetting any other part of VV5430. Resets video logic on the falling edge of the SIN pulse. Scan mode enable - only relevant to test mode. Gamma corrected or Linear output. LIN = 0, gamma corrected output, LIN = 1, linear output. Default is gamma. LIN = 0 can be overridden via serial interface. Lower bit of two least significant bits of device address on serial interface. Automatic exposure control. AEC = 1, auto exposure is enabled; AEC = 0 auto exposure and auto gain control are disabled. AEC = 1 can be overridden via serial interface. Automatic gain control enable. AGC = 1, auto-gain is enabled (if AEC = 1); AGC = 0, auto-gain is disabled. AGC can be overridden via serial interface. Select default video mode for power-on. CCIR = 1 for CCIR video. EIA video mode is selected when CCIR = 0. Default is CCIR if unconnected Normal or Backlit exposure control mode. BKLIT = 0, normal mode. BKLIT = 1, backlit mode. Default is normal. BKLIT state can be overridden via serial interface. See Exposure Control for details. Active low camera reset. All camera systems are reset to power-on state. Scan chain input - only relevant to test mode. Serial bus clock (input only). Must be generated by comms. host. Serial bus data (bidirectional, open drain).
20 21
SAB0 AEC
ID ID
22 23 28
AGC CCIR BKLIT
ID ID ID
29 38 39 40
RESETB SCI SCL SDA
ID ID ID BI
Key: OA- Analogue output OD- Digital output OD-Digital output with internal pull-down BI - Bidirectional IA ID ID Analogue input Digital input Digital input with internal pull-up
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Video Standards
VV5430
4.
Video Standards
The VV5430 has 2 different video format modes, producing CCIR or EIA standard composite Monochrome video output. Line standards and frequencies are as follows:
Video Mode CCIR EIA
Format
Image (Pixels)
Crystal Frequency
CCIR pin
4:3 4:3
384 x 287 320 x 243
14.7456 MHz 12.0000 MHz
1 0
Table 7 : VV5430 Video Modes 4.1 Video Signal Characteristics
The following table summarises the composite video output levels (AVO) for the two standards, which are graphically illustrated on the following pages:
Symb ol
VSync Vblank Vblack
Parameter
CCIR, EIA Sync. level CCIR, EIA Blanking level CCIR Black level EIA Black level
Min.
Typ .
0.3 0.9 0.9 1.0 2.3 2.4
Max.
Unit s
V V V V V V
Notes
DC reference level
VSat
CCIR Saturation level EIA Saturation level
Peak White; AVO clipped at this level
Table 8 : Video Timing Parameters Note: All measurements are made with AVO driving one 75 load.
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VV5430
Video Standards
CCIR Timing Diagram
0.3 { line blank 0.250.1s line sync. 0.05s
line time reference point line period H = 64s line sync. 4.7s back porch 5.8s
rise times (10% - 90%)
front porch 1.5s 2.3v
peak white level
0.9v
black & blanking level sync. level
0.3v
Figure 2 : CCIR composite video line-level timing
frame start field 0 2.5H field 1 2.5H 2.5H
26H SL
field 1 2.5H
field 2 2.5H 2.5H
25H
Figure 3 : CCIR composite video signal - field level timing
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Video Standards
VV5430
EIA Timing Diagrams
blank 0.3 {line sync. 0.250.1s line 0.05s
line time reference point line period H = 63.5s line sync. 4.83s back porch 4.00s
rise times (10% - 90%)
front porch 1.33s
peak white level
2.4v
1.0v black level 0.9v 0.3v blanking level sync. level
Figure 4 : EIA composite video signal - line level timing
frame start field 0 field 1 3H 3H
3H
19H field 1 field 2 3H 3H
3H
20H
Figure 5 : EIA composite video signal - field level timing
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VV5430
Control Signals for Image Digitisation
5.
Control Signals for Image Digitisation
The VV5430 sensor can be used with an Analog-to-Digital Converter (ADC) and the necessary logic to form an image capture and processing system. The camera provides an analogue video output together with digital signals to qualify this output and synchronise image capture. The signals provided for image capture are the following:-
* PV,PVB: (Pixel Valid, PV Bar) Complementary signals, their leading edges qualify valid pixel levels. * LST: (Line STart) The rising edge signals the start of a visible line. * FST: (Field STart) The rising edge signals the start of a field. * ODD: Identifies an odd field within a frame. * CPE (Clock Pulse Enable): Disables generation of PV/PVB and LST signals. The state of this pin is sampled only during a system reset. Its state after reset can be overridden via the serial interface using Set-up Code_2.
The following diagram illustrates the relative timing of the image capture signals. Scale is not actual but edge succession is preserved.
FST ODD LST AVO PV
PVB Tfst Tblank Tporch Tphd Tpv Tfield Tlst Tpsu Todd Tline
Figure 6 : Frame Capture signal timing
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Control Signals for Image Digitisation
VV5430
5.1
Image Capture Control Signal Timing
The time intervals given are correct for the recommended crystals:
Name
Crystal Frequency (FCKIN) Pixel clock period (Tpck = 2/FCKIN) PV (Pixel clock) mark:space PV high period (Tpv = Tpck/2) Even (first) field period (Tfield) Odd (second) field period (Tfield) FST duration (TFST) Line period (T line) LST duration (TLST) First visible line delay (Tblank) First visible pixel delay (Tporch) Visible line period
CCIR
14.7456 MHz 135.63 nsec 1:1 67.82 nsec 20.032 msec (313 x Tline) 19.968 msec (312 x Tline) 7.73 sec (57 x Tpck) 64.0 usec (472 x Tpck) 4.61 sec (34 x Tpck) 704.949 sec (11xTline + 7xTpck) 10.58 sec (78 x Tpck) 52.083 sec (384 x Tpck) 33.9 nsec 30nsec 21.700 msec (160 x Tpck)
EIA
12.0000 MHz 166.67nsec 1:1 83.34 nsec 16.7005 msec (263 x Tline) 16.637 msec (262 x Tline) 6.1 sec (45 x Tpck) 63.5 sec (381 x Tpck) 4.66 sec (28 x Tpck) 762.833sec (12xTline + Tpck) 8.833 sec (53 x Tpck) 53.333 sec (320 x Tpck) 41.7nsec 40nsec 11.500 msec (69 x Tpck)
Max AVO to PV setup time (Tpsu) Min. PV to AVO hold time (Tphd) ODD to FST rise (TODD)
Table 9 : Signal Timing
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VV5430
Shuffle Modes
6.
Shuffle Modes
The pixels in the VV5430 sensor array can be output to AVO as alternate columns and rows by setting bits 5 and 6 in the Setup Code_1 register (header code 0001 - see Serial Interface for details). This has the effect of generating two, or four, identical low resolution images in one field:
Unshuffled Image
Horizontal Shuffle
Vertical Shuffle
Hor. + Vert. Shuffle
When this facility is combined with AVO Enable selected for the appropriate quarter, it is possible to display the images from four separate cameras on one monitor. In order to achieve four identical images in one frame (from one sensor), bits 5 and 6 of Setup Code_1 must both be set via the serial interface, that is HSHUFFLE=1 and VSHUFFLE=1. The former interleaves odd and even pixel lines in the image, and the latter interleaves pixel columns. OE[0..2] can then Enable AVO output for any one quarter of the display field.
6.1
Quarter mode output
The VV5430 video output can be Enabled in different parts of the standard field by programming bits 9..11 of Setup Code_2, that is CE[0..2]; when not enabled, the AVO output is Tristated, that is floating at high impedance. Thus, a number of different sensor AVO outputs can be connected together and selectively enabled. This feature, together with bus addressing of up to four VV5430s on one serial link, is intended for multi-sensor systems that, in conjunction with bits 5,6 of Setup Code_1, enable the images from up to four cameras to be displayed on a single monitor. By programming CE[0..2] different areas of the field can be enabled:. Pixels Lines Sync Sync + Blanking
Q1
Q2
Image subdivided into 4 quarters : CCIR: 384 pixels x 287 lines: Q1,Q2 = 192 x 142 Q3, Q4 = 192 x 142
Q3
Q4
EIA: 320 pixels x 243 lines: Q1,Q2 = 160 x 120 Q3, Q4 = 160 x 120
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Shuffle Modes
VV5430
The effect of OE[0..2] on AVO output is summarised in the following table:
OE[2]
0 0 0 0 1 1 1 1
OE[1]
0 0 1 1 0 0 1 1
OE[0]
0 1 0 1 0 1 0 1
Regions where AVO is enabled
All (Normal operation) None (AVO permanently tristate) Sync only Sync plus Q1 image Q1 Q2 Q3 Q4
Table 10 : AVO Enable selection
Since each of the horizontal `halves' of the frame is only 142 lines (CCIR) or 120 lines (EIA), there is a `black band' of three lines separating the top half from the bottom half. Similarly, for timing purposes, there is a two pixel vertical black band separating the left and right halves of the frame. (See the timing diagram below.)
6.2
Quarter mode line timing.
Standard Line
Left Quarter
Right Quarter t1 t4 t2 t3
Pixel timings for AVO 1/4 Mode:
CCIR Description #t pck cycles
1 190
EIA Time (us)
0.1356
pck cycles
1 158
Time (us)
0.1667 26.0052
Left quarter Line Delay Duration of left quarter line
t1
25.4928
Table 11 : Pixel Timings for 1/4 mode
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VV5430
Shuffle Modes
CCIR Description #t pck cycles
2 190 t3 t4 1 384
EIA Time (us)
0.2713
pck cycles
2 158 1 320
Time (us)
0.3333 26.0052 0.1667 53.3440
Inter-quarter Interval Duration of right quarter line Right quarter border Duration of standard SI
t2
25.4928 0.1356 52.0704
Table 11 : Pixel Timings for 1/4 mode
In addition there are line level signals to identify the top and bottom half of the active video area of the field: .
Description CCIR
Top half of field Bottom half of field
Start line EIA
First active line Active line 124
Number of lines CCIR
142 142
EIA
120 120
First active line Active line 145
Table 12 : Line Timings for 1/4 mode
There is a `black band' of three video lines between the valid lines in the top half of the field and the valid lines in the bot tom half of the field. This ensures that both halves of the field are the same size and provides a horizontal frame line. The line level timing described above also provides a two pixel vertical black line, hence the four quarters appear to be `framed' in the display.
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Exposure Control
VV5430
7.
Exposure Control
Automatic exposure and gain control ensure operation of the VV5430 over a wide range of lighting conditions. Automatic black level control and optional `Backlit' mode further ensure consistent picture quality. The devices control exposure over a range of 99,000:1 in EIA mode and 146,000:1 in CCIR mode, and operates at illumination levels as low as 0.5 lux. Note: The System Clock can be divided by up to eight times to further increase sensitivity by extending the exposure time. This, of course, also reduces the frame rate to non-standard values. Automatic exposure and gain control are enabled with AEC=1 (pin 21) and AGC=1 (pin22), but can be inhibited via the serial interface (Setup Code_1). However, If AEC is inhibited by pin 21, AGC is also inhibited and the serial interface has no control. Inhibiting AEC or AGC via the serial interface, or by taking pin 21 or 22 low, freezes the current value(s) for these, which can then be altered by writing to the exposure and gain control registers. (See Serial Interface for details.)
Note: The timing of exposure and gain control messages on the serial interface is very important. External values for exposure
and gain are only applied at the start of a frame, and the serial interface must be paused until the new values are installed--no further communications will be accepted during this time.
7.1
Automatic Exposure Control (AEC)
Automatic exposure control is achieved by varying pixel current integration time according to the average light level on the sensor. This integration time can vary from one pixel clock period to one frame period. Pixels above a threshold white level are counted every frame, and the number at the end of the frame defines the image as overexposed, above average, correctly exposed, below average or underexposed. If the image is other than correctly exposed, a new value for integration time is calculated and applied for the next frame. Corrections are either 1/8 or 1/64, depending upon the degree of over or under exposure. If the exposure value is close to its limit (12% below max. or 25% above min.), then gain is increased or decreased by one step and exposure is set to midway in its range. Exposure is then controlled as normal.
7.2
Automatic Gain Control (AGC)
The VV5430 automatically increases the system gain of its output stage if with the current gain setting and maximum exposure the image is too dark. Gain can be varied from x1 to x16 in times-two steps, giving five different gain settings. If the scene is too dark and the integration period has almost reached its maximum value, the gain value is incremented by one step (times two). In the same frame period the exposure value is divided by two, halving the integration period. The exposure controller then increases the exposure value as necessary. Similarly if the image is too bright and the integration period is short then gain will be reduced by one step (divide by two) and the exposure value will be doubled. The exposure controller can then adjust the exposure value as necessary to provide a correctly exposed image. Increasing gain is limited to a programmable upper limit, for which the default value is x8. The gain upper limit is programmed by setting bits [0..3] with header code 0101, when AGC=1. If Automatic Gain Control is inhibited (AGC=0), these registers are used instead to select a gain setting up to x16.
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Exposure Control
7.3
Backlit Mode
The VV5430 can be configured to operate in two auto-exposure modes, selected by the BKLIT pin (pin28) state, or via the serial interface (Setup Code_1, bit 0). The default mode (BKLIT = 0) provides exposure control for normally illuminated scenes. For scenes where a bright background can cause the foreground subject to be severely under exposed, the `Backlit' mode (BKLIT = 1) offers superior performance. `Backlit Mode' (BKLIT=1) operates by using a higher threshold level for the exposure control comparator over the central area of an image, which is therefore exposed for longer and so enhanced. The area in which the higher comparator threshold is used when BKLIT=1 is illustrated below:
Normal operation (BKLIT=0) 10%
Higher threshold area (BKLIT=1)
30%
80%
25%
80% 90% 25% 75% Higher Threshold
Visible image
Exposure control area
Figure 7 : Backlit exposure region
Note: The threshold level used for the central area is a preset mutiple of the normal mode reference level, and is not alterable. In some circumstances this may not be sufficient difference to cause a noticable effect on the overall exposure of the image.
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Serial Communication
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8.
Serial Communication
The VV5430 includes a full duplex (two-wire) serial interface, and can be controlled and configured by a host processor. The base bus address for the VV5430 is 20H, but the two least significant bits of the address (SAB0, SAB1) can be selected by hard-wiring pins 20 and 16. This allows up to four separate camera devices to be controlled on one serial link, which, for example, makes multiplexing of camera outputs possible. The serial interface reads or writes data to a set of Registers that define the characterisation of the sensor, and control certain operations.
8.1
Serial Communication Protocol
The host must perform the role of a communications master and the camera acts as either a slave receiver or transmitters communication between host and camera takes the form of three or five byte messages of 8-bit data, with a maximum serial clock (SCL) frequency of 100kHz. Since the serial clock is generated by the host, the host determines the data transfer rate. The host processor initiates a message by forcing both Serial Data (SDA) and Serial Clock (SCL) low. The first byte addresses the required device, and defines either a READ message (four bytes to follow) or a WRITE message (two bytes to follow). After the camera has acknowledged a valid address (ACK, bit 9 of SCL), the host then either reads four bytes of data from the camera or transmits a further two bytes to the camera. The data transfer protocol on the bus is illustrated below:
Start condition
SDA MSB SCL S
Read/Write bit
Acknowledge from receiver
1
2
7
8
9
ACK
1
2
3-8
9
ACK
P
Stop condition Figure 8 : Data Transfer Protocol
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Serial Communication
stop
start
start
stop
SDA
...
Tbuf Tlo Tr Tf Thd;sta
SCL
Thd;sta Thd;dat Thi
...
Tsu;dat Tsu;sta Tsu;sto
Note: All values referred to the minimum input level (high) = 3.5V, and maximum input level (low) = 1.5V
Parameter
SCL clock frequency Bus free time between a stop and a start Hold time for a repeated start LOW period of SCL HIGH period of SCL Set-up time for a repeated start Data hold time Data Set-up time Rise time of SCL, SDA Fall time of SCL, SDA Set-up time for a stop Capacitive load of each bus line (SCL, SDA)
Symbol
Fscl Tbuf Thd;sta Tlo Thi Tsu;sta Thd;dat Tsu;dat Tr Tf Tsu;sto Cb
Min. 0 4.7 4.0 4.7 4.0 4.7 01 250 4.0 -
Max. 100 1000 300 100
Unit kHz s s s s s s ns ns ns s pF
1. The VV5430 internally provides a hold time of at least 300ns for the SDA signal (referred to the minimum input level (high) of the SCL signal) to bridge the undefined region of the falling edge of SCL Table 13 : Serial Interface Timing Characteristics
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Read data from camera
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9.
Read data from camera
Information describing the current configuration and the current exposure values can be read from the camera. The data is formed into four bytes of 8 bits. Each pair of bytes is considered to be a data word and is read out msb first.
Read = 1
Camera acknowledge (valid address) Master acknowledge
R/ W
S
ADDRESS[7:1]
A
DATA[31:24]
A
DATA[23:16]
A
001 0 0 x x 1
Master acknowledge
DATA[15:8]
A
DATA[7:0]
AP
Figure 9 : Read Data Format
The following tables defines the information contained in the read messages. By default, the Primary Read Data is accessed; only if a Secondary Read Select bit is set in Setup Code_2 (header code 0010) is the Secondary information read.
Primary Read Data:
Secondary Read Data:
Bit
31 - 23 22 - 14 13 - 10 9 8 7 6 5 4 3-0
Function
Coarse Exposure Value (9 bits) Fine Exposure Value (9 bits) Gain Value (4 bits) Auto Exposure Control on/off Internal Black Calibration on/off Auto Gain Control on/off Gamma or Linear Video Output Normal or Backlit mode1 Undefined Camera Type ID Code (4 bits)
Bit
31 - 18 17 16 - 0
Function
Undefined Black Level monitor in progress White Pixel count (17 bits)
1. Bit 5 of the Primary Read message only reflects the state of the BKLIT pin, not the combined result of the pin and the serial interface BKLIT control bit.
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Write to Camera
10. Write to Camera
Information to be communicated from host to camera consists of configuration data (for example automatic gain control ON), and parametric information (for example sensor integration time). The write data is formed into two bytes. A 4-bit Header Code in the first byte is used by the camera to determine the destination of the 12-bit message following the header.
Write = 0 S
ADDRESS[7:1]
R/ W
Camera acknowledge
A
HEADER
DATA[11:8]
A
DATA[7:0]
AP
00100xx0
Camera acknowledge (valid address)
Figure 10 : Receive Data Format
After the camera acknowledges the receipt of a valid address the host transfers the first data byte which the camera acknowledges by pulling SDA low. The second byte is then sent followed by a final acknowledge from the camera. A stop condition is produced by the host after the second message byte. As with the read procedure, the stop condition is not absolutely necessary as the camera's serial interface will reset automatically after two bytes have been received.
The valid Header Codes and their data structures are fully described in the following pages.
10.1 Timing Protocol
When an exposure or gain value has been written to the camera it is held in the interface until the camera is ready to consume the new data. For correct operation, there should be no further read or write accesses to the camera during this hold period. Normal communication between other modules connected to the serial interface will not cause problems. The minimum length of the wait period is 40ms in EIA mode and 34ms in CCIR mode from the end of the data transfer.
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10.2 Header Codes
The message can be a configuration word, an exposure, gain or calibration value. The camera's interpretation of the header code and the set-up code message are given in the table below. Defaults for each control bit are built in to the camera's reset cycle, and may be changed on-the-fly under host control.
Code
Interpretation Invalid Set-up code_1 (9 bits) Set-up code_2 (9 bits) Coarse exposure value (9 bits) Fine exposure value (9 bits) Gain control value (4 bits) Unused Unused Exposure control T1 threshold (9 bit) Exposure control T2 threshold (9 bit) Analogue control register (8 bit) Reserved Reserved Reserved Set-up code_3 (6 bits) Test mode select
Comment
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Basic funtionality options Pixel control & Read Data Set AEC=0 to enable Set AEC=0 to enable Set AGC=0 to enable
Not applicable to normal use Not applicable to normal use Not applicable to normal use Pixel synchronisation Not applicable to normal use
Table 14 : Header Codes
10.3 Message content
The following Tables contain details of the data associated with each header code, and the number of valid data bits in each of the registers. In all cases the full 12 bit message tail can be sent, the valid bits being packed to the lsb. (Normally, the unused bits would be assigned zeroes.)
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Setup Code_1
Header Code = 0001
Valid data bits: 11 The code_1 setup register is used to select different basic operating modes:
Bit
0
Function
Normal/Backlit
Default
0
Comment
Selects between normal and backlit exposure modes. The power-on default is normal mode. See Exposure Control for full description Selects between a linear (LIN=1) or gamma corrected video signal on AVO. The power-on default is gamma corrected. Allows automatic gain control to be inhibited. The current gain value selected is frozen. With AGC=0 a new gain value can be written to the gain register via the serial interface (header code 0101). Allows automatic black calibration to be inhibited. Allows automatic exposure control to be inhibited. The current exposure value selected is frozen. Note that if automatic exposure control is inhibited then automatic gain control is also disabled. With AEC=0 a new exposure value can be selected by writing to the coarse and fine exposure registers via the serial interface (header codes 0011 & 0100). Shuffles the read out of the horizontal shift register. Even columns read out together then odd columns. Shuffles the readout of the vertical shift register. Even lines read out together then odd lines. Requests a re-calibration of the black level while bit is low. System clock division: (see Note) 0,0=1; 0,1=/2; 1,0=/4; 1,1=/8 This bit must be set to 0 for correct sensor operation
1
Linear Correction enable
0
2
Auto gain control enable
1
3 4
Inhibit black calibration Auto exposure control enable
0 1
5 6 7 8 9 10 11
Horizontal shuffle enable Vertical shuffle enable Force black calibration Clock divisor DIV0 Clock divisor DIV1 Internal Register Not used
0 0 1 0 0 0 0
Table 15 : Set-up code_1 Note: Decreasing the system clock rate proportionately increases sensor sensitivity (by increasing exposure time), but also decreases frame frequency. System Clock must be x1 for standard CCIR or EIA framing.
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Setup Code_2
Header Code = 0010
Valid data bits: 12 The code_2 setup register is used to select read data, valid pixels and video output operating modes:
Bit
0 1 2 3 4 5 6 7 8 9 10 11
Function
Primary read mode (A) enable Secondary read mode (B) enable Pixel sample clock select (SEL0) Pixel sample clock select (SEL1) Not used Enable free running pixel clock Enable external pixel thresholds Not used Not used OE[0] OE[1] OE[2]
Default
0 0 CPE 0 0 0 0 0 0 0 0 0 Table 16 : Setup Code_2
Comment
Select Primary read mode A or B. Note: bits 0,1 are mutually exclusive. Pixel sample clock mode (PV/PVB). See below. MUST be set to 0 Overrides SEL0 & SEL1. Use external algorithm thresholds in exposure controller MUST be set to 0 MUST be set to 0
AVO output enable control bits [0..2]. See Shuffle Modes above for explanation.
The table below shows the function of SEL0 and SEL1 (Bit 2 and Bit 3); the default value of SEL0 is set by the CPE pin level:
Bit 3
0 0 1 1
Bit 2
0 1 0 1
Pixel Clock (PV/PVB pins) function
Disable pixel clock output Qualify full image area (as defined for CCIR or EIA) Qualify central 256 x 256 pixels (CCIR only) PV/PVB active only during interline periods of visible image lines. Note. This mode is required for digitisation of standard video output.
Table 17 : SEL0 and SEL1 bits
Coarse and Fine Exposure Values.
Header Code (coarse)
Valid data bits: 9
= 0011
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Write to Camera
Header Code (fine)
Valid data bits: 9
= 0100
The 18 bit exposure control value is formed from two 9-bit values, coarse (9 msb's) and fine (9 lsb's). For external exposure control (AEC = 0) the exposure value can be set via the serial interface (header codes 0011 and 0100). Values written that exceed the mode dependant maxima will be ignored and the maximum will be used.
Bit
0-8 0-8 9-11
Function
Coarse exposure value Fine exposure value Unused 0 0
CCIR min max
310 404 0 0
EIA min max
260 325
Comments
Header code 0011 Header code 0100
Table 18 : Exposure Values
Exposure Control Thresholds T1 and T2
Header Code (T1)
Valid data bits: 9
= 1000
Header Code (T2)
Valid data bits: 9
= 1001
The lower and upper pixel count thresholds are used by the automatic exposure controller. The power-on default values for T1 and T2 are exposure mode and video mode dependant. If the external pixel threshold control bit (bit 6 in Setup Code_2 register) is set the internal default values for T1 and T2 are overridden by the serial interface values. Note that only the most significant nine bits of each seventeen bit threshold can be controlled.
Bit
0-8 0-8 9 - 11
DAC
Lower Exposure control threshold (T1) Upper Exposure control threshold (T2) Unused
Comments
Header Code 1000 Header Code 1001
Table 19 : Pixel Count Thresholds (T1,T2)
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Gain and Gain Ceiling
Header Code = 0101
Valid data bits: 4 This register is used to select an external gain value when automatic gain control is inhibited (AGC = 0) and to set the gain ceiling while automatic gain control is active (AGC = 1).
Bit
0 1 2 3 4-11
Function
Gain value G[0] Gain value G[1] Gain value G[2] Gain Value G[3] Unused
Default
0 0 0 0
Comment
Default gain value
Default gain ceiling
Table 20 : Gain Register
The table below shows the valid gain codes.
G[3]
0 0 0 0 1
G[2]
0 0 0 1 1
G[1]
0 0 1 1 1
G[0]
0 1 1 1 1
Gain
1 2 4 8 16 Table 21 : Gain Values
Comment
Default gain value
Default gain ceiling
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Write to Camera
Analogue Control Register
Header Code = 1010
Valid data bits: 10 A number of parameters that are used to define internal operations can be altered by the serial interface:
Bit
0 1 2 3 4 5 6 7 8 9
Function
Internal Internal Internal Disable anti-blooming protection Internal Internal Enable external black reference Enable external white threshold Internal Enable binarisation of AVO output
Default
1 0 0 0 0 0 0 0 0 0
Comments
Must be set(=1) for normal op. Must be 0 for normal op. Must be 0 for normal op.
Must be 0 for normal op. Must be 0 for normal op.
Must be 0 for normal op. AVO output level is either VBLACK or VWHITE for each pixel (see Note)l
Table 22 : Control Register Note: The Threshold Level above which a pixel is deemed to be WHITE is set via the serial interface, Header Codes 1001 and 1000 (Upper and Lower Exposure Control Thresholds).
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Setup Code_3
Header Code = 1110
Valid data bits: 7 This register stores data used during sensor synchronisation and when the pixel counter in the video timing logic is reset, either at the end of a video line or when the sensor is forced to synchronise externally.
Bit
5:0
Function
Video timing pixel counter offset
Default
3
Comment
Variable offset that is added to the fixed pixel counter preset value when the counter is reset, at the end of a video line or when an external synchronisation is applied Synchronising signal to other cameras in multicamera applications (see Note)
6 11:7
Enable SNO Not used
0 0
Table 23 : Set-Up Code_3 Note: Enable SNO adjusts the timing of the FST signal (output on pin 36) to correctly synchronise external slave cameras. Alternatively, the synchronising signal for all cameras can be generated externally, which may be more useful in image processing applications.
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Example Support Circuit
11. Example Support Circuit
AVD VDD 8
REG1
2, 3, 6, 7
1 C2
+7 to +12v dc
C1
R1 C5 C3 C6
0v
C4 C7 27 34 41 1 7 13 14 15 38 30 18 23 36 33 32 37 11 12 8 9 43 6 5 C19 C18 R4 MONITOR VDD1 VDD2 DVDD AVCC AVDD VVDD 24 VSS1 VSS2 DVSS AVSS AGND SAB1 SAB0 BKLIT LIN AGC AEC VBLOOM VRT VCM DNC 47 C10 39 40 VREF2V7 DEC2V7 SCL SCL SDA RESETB CPE 35 SIN 17 CKIN 26 R3 C11 VDD VOFF/VPED 3 CKOUT 25 R2 C12 VBG C16 C15 FST PVB PV ODD AVO VGND SCI LST SCE CCIR
Component IC1 REG1 C1,C2 C3 C4 - C9,C13, C15 - C19 C10 C11, C12 C14 R1 R2 R3 R4
Value VV5430 LM78L05 0.22 F 68 F (6V Tant.) 0.1 F 4.7F 10 pF 100pF
C8
31 42 10 48 16 VDD 20 28 19 22 21 44 45 R5 C9 46
IC1 (48 pin LCC)
VV5430
AMP2 AMP1 EBCK EVWT VBLTW
5R6 10R 10M 75R
C17
Use Surface Mount components throughout.
DEC2V2 4
SDA
29
2
C13
C14
X1
1. Keep nodes Supply and Ground pins low impedance and independent 2. Video output should be referred to VGND. 3. Keep circuit components close to chip pins (especially de-coupling capacitors)
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Ordering Details
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12. Ordering Details
STMicroelectronics recommends using their Evaluation Kits for initial evaluation of sensors. For the VV5430 sensors the Evaluation Kit comprises a lensed board camera attached to an embedded microcontroller, and an LCD display in a plastic case. Buttons are provided to control the different options of the sensor in real time. In addition software is provided to allow cont rol of the sensor from a PC running Windows95, via the serial port.
Part Number
VV5430C001
Description
CCIR/EIA Enhanced Monochrome Analog Video Image Sensor, 48 pin LCC package CCIR Evaluation Kit for VV5430 sensor
Defect specification
As per Defect Specification, Section 2.2 As per Defect Specification, Section 2.2 As per Defect Specification, Section 2.2
EVK-5430-001
EVK-5430-002
EIA Evaluation Kit for VV5430 sensor
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result fr om its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics The ST logo is a registered trademark of STMicroelectronics (c) 1999 STMicroelectronics - All Rights Reserved .
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www.vvl.co.uk www.st.com
(R)
VLSI VISION LIMITED
A company of the ST Microelectronics Group
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